The present invention relates to a semiconductor memory device and, more particularly, to a technique which is effective when applied to a technology for increasing the speed and lowering the power consumption of a flash erasable type EEPROM (i.e., Electrically Erasable/Programmable Read Only Memory).
The electric flash erasable type EEPROM is a nonvolatile memory device having a function to electrically erase all memory cells formed on a chip or electrically erase a group including some of the memory cells formed on the chip, in a batch.
This flash erasable type EEPROM is disclosed on pp. 152 to 153 of IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE OF 1980, on pp. 76 to 77 of IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE of 1987 and on pp. 1,157 to 1,163 of IEEE, J. Solid-State Circuits, vol. 23 (1988).
FIG. 21 is a schematic diagram showing a sectional structure of a memory cell of an electric flash erasable type EEPROM which was disclosed in the International Electron Device Meeting of 1987. The memory cell, as shown, has a structure similar to that of an ordinary EPROM memory cell. Specifically, the memory cell is constructed of an insulated gate type field effect transistor (which will be called the "MOSFET" or merely the "transistor") having a two-layered gate structure. In FIG. 21: reference numeral 8 designates a P-type silicon substrate; numeral 11 a P-type diffusion layer formed over the silicon substrate 8; numeral 10 a lightly doped N-type diffusion layer formed over the silicon substrate 8; and numerals 9 designate N-type diffusion layers individually formed over the P-type diffusion layer 11 and the N-type diffusion layer 10, respectively. Moreover: numeral 4 designates a floating gate formed over the P-type silicon substrate 8 through a thin oxide film 7; numeral 6 a control gate formed over the floating gate 4 through the oxide film 7; numeral 3 designates a drain electrode; and numeral 5 a source electrode. In short, the memory cell, as shown, is constructed of an N-channel type MOSFET having a two-layered structure for storing information. Here, the information is stored substantially as the change in the threshold voltage in the transistor.
In the following, the memory cell will be described in a case in which the transistor for storing the information (as will be called the "memory transistor") is of the N-channel type, unless otherwise specified. The operation of programming the information in the memory cell, as shown in FIG. 21, is similar to that of the EPROM. Specifically, the programming operation is carried out by injecting the hot carriers generated in the vicinity of the drain region 9, connected with the drain electrode 3, into the floating gate 4. As a result of this programming operation, the memory transistor has its threshold voltage, as viewed from its control gate 6, raised to a higher level than that of a memory transistor which is left unprogrammed.
In the erasing operation, on the other hand, a high field is established between the floating gate 4 and the source region 9 connected with the source electrode 5, by grounding the control gate 6 to the earth and by applying a high voltage to the source electrode 5, so that the electrons stored in the floating gate 4 are extracted via the source region 9 to the source electrode 5 by making use of the tunnel phenomenon through the thin oxide film 7. As a result, the stored information is erased. In short, as a result of this erasing operation, the memory transistor has its threshold voltage lowered, as viewed from its control gate 6.
In the reading operation, the voltage to be applied to the drain electrode 3 and the control gate 6 is limited to a relatively low level so as to prevent a weak programming of the aforementioned memory cell, that is, to prevent the undesirable carrier from being injected into the floating gate 4. For example, a voltage as low as about 1 V is applied to the drain electrode 3, and a voltage as low as about 5 V is applied to the control gate 6. By detecting the magnitude of the channel current which is caused to flow through the memory transistor by applying those voltages, the information "0" or "1" stored in the memory cell is judged.